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SAMSUNG SEMICONDUCTOR CO. LTD.
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| Part No. |
S3C80F7 S3C80F9 S3C80G7
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| OCR Text |
...bit timer/counter (timer1) with two operating modes; interval mode and capture. carrier frequency generator one 8-bit counter with auto-rel...port 0 p0.0-0.3 (int0-int3) p0.4-p0.7 (int4) i/o port and interrupt control 32k-bytes rom 317-bytes ... |
| Description |
S3C8-SERIES MICROCONTROLLERS
SH2A Series, 7211 Group, Two ADC circuits, 6-ch 16-bit MTU2, 3-ch 16-bit MTU2S, Port Output Enable, 2-ch CMT, UBC, SDRAM, WAVE, 15 mA IO FP-144CV
SH2 Series, 7149 Group, Three ADC circuits, 6-ch 16-bit MTU2, 3-ch 16-bit MTU2S, Port Output Enable, 2-ch CMT, UBC, 15 mA IO FP-100U; Vcc= 4.0 to 5.5
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| File Size |
205.57K /
34 Page |
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ST Microelectronics
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| Part No. |
TDA7427A TDA7427AAD TDA7427AAD1
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| OCR Text |
...ication, the counter works in a two-stage configuration. the first stage is a swallow counter with a two modulus (:32/33) precounter. the se...port extension 0bh - - dout3 dout4 dout5 dout6 dout2 dout1 table 1. address organization tda7427a 6/... |
| Description |
AM-FM RADIO FREQUENCY SYNTHESIZER AND IF COUNTER
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| File Size |
162.72K /
21 Page |
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it Online |
Download Datasheet |
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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1310CV18-167BZXC CY7C1314CV18-167BZI CY7C1314CV18-167BZXI
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| OCR Text |
...ferred at 500 mhz) at 250 mhz two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only two input clocks for ou tp...port selects for depth expansion synchronous internally self-timed writes qdr?-ii operates with 1.... |
| Description |
18-Mbit QDR-IISRAM 2-Word Burst Architecture 2M X 8 QDR SRAM, 0.5 ns, PBGA165
18-Mbit QDR-IISRAM 2-Word Burst Architecture 512K X 36 QDR SRAM, 0.5 ns, PBGA165
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| File Size |
414.85K /
28 Page |
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it Online |
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