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    Agilent (Hewlett-Packard)
Part No. E2922B
OCR Text ...miconductor industry a fast and predictable way to setup pci-x traffic and verify pci-x protocol compliance of first silicon. the e2922b is a dedicated validation solution for test setups where full population of all available pci-x slot...
Description 133 MHz PCI-X Master Target Test Card

File Size 1,594.26K  /  11 Page

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    GS1881 GS1881-IDA GS1881-IKA GS4881 GS4981 GS4881-CTA GS4881-IDA GS4981-IKA GS4981-ITA GS4981-CDA GS4981-CKA GS4981-CTA

GENNUM[Gennum Corporation]
ETC
N.A.
Electronic Theatre Controls, Inc.
Part No. GS1881 GS1881-IDA GS1881-IKA GS4881 GS4981 GS4881-CTA GS4881-IDA GS4981-IKA GS4981-ITA GS4981-CDA GS4981-CKA GS4981-CTA GS4881-IKA GS4881-CDA GS4881-CKA GS4881-ITA GS1881-CDA GS1881-CKA GS1881-CTA GS1881-ITA GS4981-IDA
OCR Text ..., horizontal (GS4981) outputs * predictable vertical output pulse width with default trigger for non-standard video signals * 5 V to 12 V supply voltage range * pin compatible with LM1881 sync separator SELECTION CHART DESCRIPTION The GS188...
Description    Monolithic Video Sync Separators
Monolithic Video Sync Separators 单片视频同步分离

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    PALCE20V8H-10JC/4 PALCE20V8H-10PC/4 PALCE20V8H-15JC/4 PALCE20V8H-15JI/4 PALCE20V8H-15PC/4 PALCE20V8H-15PI/4 PALCE20V8H-5

Lattice Semiconductor, Corp.
Lattice Semiconductor Corporation
Part No. PALCE20V8H-10JC/4 PALCE20V8H-10PC/4 PALCE20V8H-15JC/4 PALCE20V8H-15JI/4 PALCE20V8H-15PC/4 PALCE20V8H-15PI/4 PALCE20V8H-5JC/5 PALCE20V8H-25PC/4 PALCE20V8Q-15PC/4 PALCE20V8Q-25PC/4 PALCE20V8H-7JC/5 PALCE20V8Q-15JC/4 PALCE20V8H-7PC/5 PALCE20V8Q-25JI/4 PALCE20V8H-25PI/4 PALCE20V8Q-20PI/4 PALCE20V8H-25JI/4 PALCE20V8Q-20JI/4 PALCE20V8Q-25JC/4 PALCE20V8Q-25PI/4
OCR Text ...ops power up to a logic LOW for predictable system initialization. Outputs of the PALCE20V8 depend on whether they are selected as registered or combinatorial. If registered is selected, the output will be HIGH. If combinatorial is selected...
Description EE CMOS 24-Pin Universal Programmable Array Logic EE PLD, 7.5 ns, PQCC28
EE CMOS 24-Pin Universal Programmable Array Logic EE PLD, 7.5 ns, PDIP24
KPT 19C 19#20 SKT PLUG
KPTC 6C 6#20 SKT PLUG
KPTC 4C 4#20 SKT PLUG
KPT 19C 19#20 PIN PLUG

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    Cypress Semiconductor, Corp.
Part No. CY7C371I-110AC CY7C371I-110JC CY7C371I-66JC CY7C371I-66AC
OCR Text ...cted with an extremely fast and predictable routing resource?the programmable interconnect matrix (pim). the pim brings flex- ibility, routability, speed, and a uniform delay to the intercon- nect. like all members of the f lash 370i family...
Description Flash Complex PLD 闪光复杂可编程逻辑器件

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    74HC163 74HC163D 74HC163PW 74HC163DB 74HC163N 74HCT163 74HCT163D 74HCT163DB 74HCT163N 74HCT163PW 74HC163NB 74HC163U

NXP Semiconductors
PHILIPS[Philips Semiconductors]
Part No. 74HC163 74HC163D 74HC163PW 74HC163DB 74HC163N 74HCT163 74HCT163D 74HCT163DB 74HCT163N 74HCT163PW 74HC163NB 74HC163U
OCR Text ...nput is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the set-up and hold times for the input (Dn) and parallel enable input (PE). ...
Description Presettable synchronous 4-bit binary counter; synchronous reset
Presettable synchronous 4-bit binary counter synchronous reset

File Size 86.62K  /  11 Page

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    74HC162 74HCT162

NXP Semiconductors
PHILIPS[Philips Semiconductors]
Part No. 74HC162 74HCT162
OCR Text ...nput is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the set-up and hold times for the input (Dn) and parallel enable input (PE). ...
Description Presettable synchronous BCD decade counter; synchronous reset
Presettable synchronous BCD decade counter synchronous reset

File Size 78.98K  /  11 Page

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    Actel, Corp.
Part No. RT54SX32-CQ256E A54SX16-1CQ208B A54SX16-CQ208B A54SX16-1CQ208M A54SX16-1CQ256 A54SX16-1CQ256B A54SX32-CQ256M A54SX32-1CQ256B RT54SX16-CQ208M A54SX16-CQ256M RT54SX16-CQ256
OCR Text ...ile, user programmable  highly predictable performance with 100% automatic place and route  100% resource utilization with 100% pin locking  mixed voltage support?3.3v operation with 5.0v input tolerance for low power operation  jtag ...
Description Field Programmable Gate Array (FPGA) 现场可编程门阵列(FPGA

File Size 301.43K  /  36 Page

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    PALCE20V8H-10JC_4 PALCE20V8H-15JC_4 PALCE20V8H-15JI_4 PALCE20V8H-15PC_4 PALCE20V8H-15PI_4 PALCE20V8H-25JC_4 PALCE20V8H-2

LATTICE[Lattice Semiconductor]
Part No. PALCE20V8H-10JC_4 PALCE20V8H-15JC_4 PALCE20V8H-15JI_4 PALCE20V8H-15PC_4 PALCE20V8H-15PI_4 PALCE20V8H-25JC_4 PALCE20V8H-25JI_4 PALCE20V8H-25PC_4 PALCE20V8H-25PI_4 PALCE20V8H-5JC_5 PALCE20V8H-7JC_5 PALCE20V8Q-15JC_4 PALCE20V8Q-15PC_4 PALCE20V8Q-20JI_4 PALCE20V8Q-20PI_4 PALCE20V8Q-25JC_4 PALCE20V8Q-25PC_4 PALCE20V8Q-25PI_4 PALCE20V8 PALCE20V8H-7PC_5 PALCEB20V8H-10JC_4 PALCE20V8H-10PC_4 PALCE20V8Q-25JI_4
OCR Text ...ops power up to a logic LOW for predictable system initialization. Outputs of the PALCE20V8 depend on whether they are selected as registered or combinatorial. If registered is selected, the output will be HIGH. If combinatorial is selected...
Description EE CMOS 24-Pin Universal Programmable Array Logic

File Size 353.63K  /  27 Page

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