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  lvcmos Datasheet PDF File

For lvcmos Found Datasheets File :: 9359    Search Time::2.047ms    
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    PCK953BD PCK953

NXP Semiconductors
PHILIPS[Philips Semiconductors]
Part No. PCK953BD PCK953
OCR Text ...ents. All control inputs accept lvcmos or LVTTL compatible levels, while the outputs provide lvcmos levels with the ability to drive terminated 50 transmission lines. For series terminated 50 lines, each of the PCK953 outputs can drive tw...
Description 50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver

File Size 65.55K  /  8 Page

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    FX-400 FX-40011

Vectron International, Inc
Part No. FX-400 FX-40011
OCR Text ...o 4 ext.-muxed clock inputs ? lvcmos / lvds / lvpecl inputs compatible ? di" erential lvpecl /lvds or lvcmos output ? lock detect / loss of signal alarms ? output disable ? 20.3 x 13.7 x 5.1 mm smt package ? rohs/lead free compliant ...
Description Low Jitter Frequency Translator

File Size 620.58K  /  10 Page

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    ICS843004 ICS843004AG ICS843004AGT

ICST[Integrated Circuit Systems]
Part No. ICS843004 ICS843004AG ICS843004AGT
OCR Text ...crystal oscillator interface or lvcmos/LVTTL single-ended input * Supports the following output frequencies: 212.5MHz, 187.5MHz, 159.375MHz, 156.25, 106.25MHz, 53.125MHz * VCO range: 560MHz - 680MHz * RMS phase jitter @ 212.5MHz, using a 26...
Description FEMTOCLOCKS lvcmos/CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
FEMTOCLOCKS⑩ lvcmos/CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER

File Size 288.06K  /  16 Page

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    Hynix
Part No. HY5MS7B2BLF
OCR Text ...age levels are compatible with lvcmos. read and write accesses to the low power ddr sdram (mob ile ddr sdram) are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed se...
Description Mobile DDR SDRAM 512M

File Size 1,600.75K  /  61 Page

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    AD9573-EVALZ AD9573ARUZ

Analog Devices
http://
Part No. AD9573-EVALZ AD9573ARUZ
OCR Text ...os for 100 mhz, 33.33 mhz lvds/lvcmos output format integrated loop filter space saving 4.4 mm 5.0 mm tssop 0.235 w power dissipation 3.3 v operation applications line cards, switches, and routers cpu/pcie applications low jitter...
Description PCI-Express Clock Generator IC, PLL Core, Dividers, Two Outputs

File Size 212.01K  /  12 Page

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    ICSSSTV16857 ICSSSTV16857YL-T ICS16857 ICSSSTV16857YG-T ICSSSTV16857YGLF-T

Integrated Circuit Syst...
ICST[Integrated Circuit Systems]
NXP Semiconductors N.V.
DOMINANT Opto Technologies Sdn. Bhd.
Part No. ICSSSTV16857 ICSSSTV16857YL-T ICS16857 ICSSSTV16857YG-T ICSSSTV16857YGLF-T
OCR Text ...t for the RESET# input which is lvcmos. Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#. Data is triggered on the positive edge of CLK. CLK# must be used to maintain noise margins. RESET# must be supporte...
Description SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48 0.240 INCH, 0.50 MM PITCH, TSSOP-48
DDR 14-Bit Registered Buffer 复员14位注册缓冲区

File Size 112.85K  /  8 Page

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    ICSSSTV16859 ICSSSTV16859YK

ICST[Integrated Circuit Systems]
Part No. ICSSSTV16859 ICSSSTV16859YK
OCR Text ...t for the RESET# input which is lvcmos. Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#. Data is triggered on the positive edge of CLK. CLK# must be used to maintain noise margins. RESET# must be supporte...
Description DDR 13-Bit to 26-Bit Registered Buffer

File Size 231.88K  /  8 Page

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