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Part No. |
MT41J1G4THD-15 MT41J512M8THD-187E MT41J512M8THD-15
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OCR Text |
...e[1:0] input clock enable: cke enables (registered high) and di sables (registered low) internal circuitry and clocks on the dram. the specific circuitr y that is enabled/disabled is dependent upon the ddr3 sdram configuration and opera... |
Description |
64M X 4 DDR DRAM, 1.5 ns, PBGA78 32M X 8 DDR DRAM, 1.87 ns, PBGA78 32M X 8 DDR DRAM, 1.5 ns, PBGA78
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File Size |
455.80K /
14 Page |
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it Online |
Download Datasheet |
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Part No. |
MT41J1G4THD-187ED MT41J1G4THU-187A MT41J1G4THU-15A
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OCR Text |
...e[1:0] input clock enable: cke enables (registered high) and di sables (registered low) internal circuitry and clocks on the dram. the specific circuitr y that is enabled/disabled is dependent upon the ddr3 sdram configuration and opera... |
Description |
1G X 4 DDR DRAM, PBGA78 1G X 4 DDR DRAM, PBGA82
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File Size |
455.67K /
14 Page |
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it Online |
Download Datasheet |
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Integrated Device Technology, Inc.
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Part No. |
IDT7008
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OCR Text |
... standby: 1mw (typ.) dual chip enables allow for depth expansion without external logic high-speed 64k x 8 dual-port static ram idt7008s/l notes: 1. busy is an input as a slave (m/ s = v il ) and an output when it is a master (m/ s = v ... |
Description |
64K x 8 Dual-Port RAM
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File Size |
241.15K /
20 Page |
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it Online |
Download Datasheet |
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Price and Availability
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