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W921C844 OX0368 ZJY51R5 AS5247 ASS355BD BCR114 354203 00312
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    INTERSIL[Intersil Corporation]
Part No. 5962-9052502MQA HD3-6402R-9Z HD3-6402R-9 HD-6402 HD-6402_05 HD-640205 HD-6402-05
OCR Text ...d before the last character was transferred to the receiver buffer register. A high level on STATUS FLAGS DISABLE forces the outputs PE, FE, OE, DR, TBRE to a high impedance state. The Receiver register clock is 16X the receiver data rate. ...
Description CMOS Universal Asynchronous Receiver Transmitter (UART)

File Size 213.94K  /  7 Page

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    ATA6827

ATMEL Corporation
Part No. ATA6827
OCR Text ...bit control word with LSB being transferred first Serial clock input; 5-V CMOS logic level input with internal pull down; controls serial data input interface and internal shift register (fmax = 2 MHz) Ground; reference potential Serial dat...
Description High Temperature Triple Half-bridge Driver with Serial Input Control

File Size 165.91K  /  15 Page

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    ATA6831 ATA6831-PIPW ATA6831-PIQW ATA6831-PISW

ATMEL Corporation
Part No. ATA6831 ATA6831-PIPW ATA6831-PIQW ATA6831-PISW
OCR Text ... a 16-bit control word with LSB transferred first Serial clock input; 5V CMOS logic level input with internal pull-down; controls serial data input interface and internal shift register (fmax = 2 MHz) PWM input; 5V CMOS logic level input wi...
Description Triple Half-bridge Driver with SP and PWM

File Size 169.71K  /  17 Page

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    ATA6832

ATMEL Corporation
Part No. ATA6832
OCR Text ... a 16-bit control word with LSB transferred first Serial clock input; 5V CMOS logic level input with internal pull-down; controls serial data input interface and internal shift register (fmax = 2 MHz) PWM input; 5V CMOS logic level input wi...
Description High Temperature Triple Half-bridge Driver with SPI and PWM

File Size 167.11K  /  16 Page

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    IDT
ETC[ETC]
Part No. IDT77010L155PQF IDT77010
OCR Text ...ation UTOPIA receive cells are transferred to the DPI-4 interface one cell at a time. The DPI-4 clock rate is twice the frequency of receive UTOPIA clock. DPI-4 transmit cells are transferred to the UTOPIA transmit bus one cell at a time. ...
Description DPI to UTOPIA Level 1 Interface **NOT RECOMMENDED FOR NEW DESIGNS**
Data Path Interface to Utopia Level 1 Translation Device

File Size 138.33K  /  21 Page

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    EMMICRO[EM Microelectronic - MARIN SA]
Part No. V3023 V3023SO28B V3023SO28A
OCR Text ...M (addr. 20 to 28 hex) and then transferred to the reserved clock area using the clock command followed by a write. The digital trimming register must then be initialised by writing 210 (D2 hex) to it, if Frequency Tuning is not required. A...
Description Very Low Power 8-Bit 32 kHz RTC Module with Digital Trimming, User RAM and High Level Integration

File Size 605.50K  /  15 Page

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    FM25V01-G FM25V01-GTR

Cypress Semiconductor
Part No. FM25V01-G FM25V01-GTR
OCR Text ...ediately after it has been transferred to the devic e. the next bu s cycle may commence without the need for data polling . t he product offers v ery high write endurance , orders of magnitude more endurance tha...
Description    128Kb Serial 3V F-RAM Memory

File Size 363.08K  /  18 Page

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    TI
Part No. TPA5050
OCR Text ...d circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the...
Description Stereo Digital Audio Lip-Sync Delay With I2C Control

File Size 478.28K  /  17 Page

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