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				Lattice Semiconductor Corp
Part No.	M4A5-64_32-10JC
OCR Text	... for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention....
Description	IC,COMPLEX-EEPLD,64-CELL,10NS PROP DELAY,LDCC,44PIN,PLASTIC
File Size	740.58K / 61 Page	View it Online	Download Datasheet

				NXP Semiconductors PHILIPS[Philips Semiconductors]
Part No.	74LV377 74LV377PWDH 74LV377D 74LV377DB 74LV377N 74LV377PW
OCR Text	... the LOW-to-HIGH transition for predictable operation. CONDITIONS CL = 15pF VCC = 3.3V 3 3V TYPICAL 13 77 3.5 20 UNIT ns MHz pF pF Notes 1 and 2 NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in W) VCC2 ...
Description	Octal D-type flip-flop with data enable; positive edge-trigger
File Size	117.85K / 12 Page	View it Online	Download Datasheet

				PHILIPS[Philips Semiconductors] NXP Semiconductors N.V.
Part No.	74ALS74A 74ALS74AD 74ALS74ADB 74ALS74AN 74ALS74
OCR Text	...igh transition of the clock for predictable operation. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be c...
Description	Dual D-type flip-flop with set and reset ALS SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
File Size	50.56K / 10 Page	View it Online	Download Datasheet

				Philips
Part No.	74HC259 74HC259D 74HC259DB 74HC259N 74HC259PW 74HCT259N 74HCT259D 74HCT259PW 74HCT259DB
OCR Text	...nput is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the data set-up and hold times for the D input to LE input. The shaded area...
Description	74HC/HCT259; 8-bit addressable latch
File Size	78.15K / 11 Page	View it Online	Download Datasheet

				PHILIPS[Philips Semiconductors] NXP Semiconductors
Part No.	I74F74N I74F74D 74F74 N74F74N N74F74D 74F74_2
OCR Text	...igh transition of the clock for predictable operation. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be c...
Description	From old datasheet system Dual D-type flip-flop
File Size	83.47K / 8 Page	View it Online	Download Datasheet

				NXP Semiconductors PHILIPS[Philips Semiconductors]
Part No.	74ALS377 74ALS377D 74ALS377DB 74ALS377N
OCR Text	...ow-to-High clock transition for predictable operation. TYPICAL SUPPLY CURRENT (TOTAL) 15mA PIN CONFIGURATION E Q0 1 2 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 CP D0 3 D1 4 Q1 Q2 5 6 D2 7 D3 8 Q3 9 GND 10 SF0...
Description	Octal D flip-flop with enable
File Size	122.39K / 10 Page	View it Online	Download Datasheet

				MOTOROLA[Motorola, Inc] MOTOROLA[Motorola Inc]
Part No.	SN54LS298J 74LS298 SN74LS298N SN54LS298 SN74LS298D
OCR Text	...LOW transition of the clock for predictable operation. TRUTH TABLE INPUTS S I I h h I0 I h X X I1 X X I h OUTPUT Q L H L H L = LOW Voltage Level H = HIGH Voltage Level X = Don't Care I = LOW Voltage Level one setup time prior to the ...
Description	QUAD 2-INPUT MULTIPLEXER WITH STORAGE
File Size	187.63K / 6 Page	View it Online	Download Datasheet

				LATTICE[Lattice Semiconductor]
Part No.	MACH4 M4LV-128_64-7VC M4LV-128_64-7VI M4-256_128-12YC M4-256_128-12YI M4-128N_64-15JC M4LV-96_48-7VI M4-128_64-10VC M4-128_64-10VI M4-128_64-10YC M4-128_64-10YI M4-128_64-12VC M4-128_64-12VI M4-128_64-12YC M4-128_64-12YI M4-128_64-15VC M4-128_64-15YC M4-128_64-18VI M4-128_64-18YI M4-128_64-7VC M4-128_64-7VI M4-128_64-7YC M4-128_64-7YI M4-128N_64-10JC M4-128N_64-10JI M4-128N_64-12JC M4-128N_64-12JI M4-128N_64-18JI M4-128N_64-7JC M4-128N_64-7JI M4-192_96-10VC M4-192_96-10VI M4-192_96-12VC M4-192_96-12VI M4-192_96-15VC M4-192_96-18VI M4-192_96-7VC M4-192_96-7VI M4-256_128-10AC M4-256_128-10AI M4-256_128-10YC M4-256_128-10YI M4-256_128-12AC M4-256_128-12AI M4-256_128-15AC M4-256_128-15YC M4-256_128-18AI M4-256_128-18YI M4-256_128-7AC M4-256_128-7AI M4-256_128-7YC M4-256_128-7YI M4-32_32-10JC M4-32_32-10JI M4-32_32-10VC M4-32_32-10VC48 M4-32_32-10VI M4-32_32-10VI48 M4-32_32-12JC M4-32_32-12JI M4-32_32-12VC M4-32_32-12VC48 M4-32_32-12VI M4-32_32-12VI48 M4-32_32-15JC M4-32_32-15VC M4-32_32-15VC48 M4-32_32-18JI M4-32_32-18VI M4-32_32-18VI48 M4-32_32-7JC M4-32_32-7JI M4-32_32-7VC M4-32_32-7VC48 M4-32_32-7VI M4-32_32-7VI48 M4-64_32-10JC M4-64_32-10JI M4-64_32-10VC M4-64_32-10VC48 M4-64_32-10
OCR Text	... for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The MACH 4 devices offer densities ranging from 32 to 256 macrocells with 100% utilization and 100% pin-out retention. The...
Description	High Performance E 2 CMOS In-System Programmable Logic
File Size	468.07K / 46 Page	View it Online	Download Datasheet

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