|
|
|
CYPRESS[Cypress Semiconductor]
|
Part No. |
CY7C1219F-133AC CY7C1219F
|
OCR Text |
...s controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, ... |
Description |
1-Mb (32K x 36) Pipelined DCD Sync SRAM 1-Mbit (32K x 36) Pipelined DCD Sync SRAM
|
File Size |
330.29K /
15 Page |
View
it Online |
Download Datasheet |
|
|
|
Cypress Semiconductor Corp. CYPRESS[Cypress Semiconductor]
|
Part No. |
CY7C1223F-133AC CY7C1223F
|
OCR Text |
...s controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, ... |
Description |
2-Mb (128K x 18) Pipelined DCD Sync SRAM
|
File Size |
325.58K /
15 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|