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ICS
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| Part No. |
ICS8521I
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| OCR Text |
hstl FANOUT BUFFER
FEATURES
* 9 hstl outputs * Selectable differential CLK, nCLK or LVPECL clock inputs * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, hstl, SSTL, HCSL * PCLK, nPCLK supports the followi... |
| Description |
Low Skew, 1-to-9, Differential-to- hstl Fanout Buffer. Industrial Temp. VOHmax=1.4V. (P)
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| File Size |
115.29K /
14 Page |
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ICS
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| Part No. |
ICS8521
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| OCR Text |
hstl FANOUT BUFFER
FEATURES
* 9 hstl outputs * Selectable differential CLK, nCLK or LVPECL clock inputs * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, hstl, SSTL, HCSL * PCLK, nPCLK supports the followi... |
| Description |
Low Skew, 1-to-9, Differential-to- hstl Fanout Buffer. VOHmax=1.4V
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| File Size |
267.52K /
15 Page |
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it Online |
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IDT
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| Part No. |
IDT72T72115 IDT72T7295 IDT72T72105
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| OCR Text |
...ation of Clocks User selectable hstl/LVTTL Input and/or Output Read Enable & Read Clock Echo outputs aid high speed operation User selectable Asynchronous read and/or write port timing 2.5V LVTTL or 1.8V, 1.5V hstl Port Selectable Input/Oup... |
| Description |
2.5 VOLT HIGH-SPEED TeraSync? FIFO 72-BIT CONFIGURATIONS
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| File Size |
517.07K /
53 Page |
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it Online |
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IDT
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| Part No. |
IDT72T51546
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| OCR Text |
...electable i/o: 2.5v lvttl, 1.5v hstl, 1.8v ehstl ? ? ? ? ? default multi-queue device configurations ? idt72t51546 : 1,024 x 36 x 32q ? idt72t51556 : 2,048 x 36 x 32q ? ? ? ? ? 100% bus utilization, read and write on every clock cycle ? ? ?... |
| Description |
(IDT72T51546 / IDT72T51556) 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES
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| File Size |
647.58K /
64 Page |
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it Online |
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XILINX
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| Part No. |
XC2C128
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| OCR Text |
... levels * SSTL2-1, SSTL3-1, and hstl-1 I/O compatibility - Hot pluggable
Description
The CoolRunner-II 128-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communica... |
| Description |
CoolRunner-II CPLD
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| File Size |
129.03K /
17 Page |
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it Online |
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Sony
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| Part No. |
CXK77B1841AGB CXK77B3641AGB
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| OCR Text |
...dance control resister input in hstl LW SRAMs. 5. Pad Locations 3J and 5J are true no-connects. However, they are defined as VREF input reference voltage inputs in hstl LW SRAMs.
4Mb, Sync LW, LVTTL, rev 1.2
2 / 28
September 24, 19... |
| Description |
4Mb Late Write LVTTL High Speed Synchronous SRAMs (128K x 36 or 256K x 18 Organization)
From old datasheet system
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| File Size |
221.04K /
28 Page |
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it Online |
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IDT
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| Part No. |
IDT72T51258 IDT72T51268 IDT72T51248
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| OCR Text |
...0in to x10out All I/O is LVTTL/ hstl/ ehstl user selectable 3.3V tolerant inputs in LVTTL mode
* * * * * * * * * * * * * * * *
ERCLK & EREN Echo outputs on read port Write Chip Select WCS input for write port Read Chip Select RCS inpu... |
| Description |
2.5V MULTI-QUEUE DDR FLOW-CONTROL DEVICES
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| File Size |
471.07K /
55 Page |
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it Online |
Download Datasheet |
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