| |
|
 |
Renesas Electronics Corporation
|
| Part No. |
ADCMB-HSFMC-EV1Z
|
| OCR Text |
...vides deterministic latency and multi-chip time alignment support to satisfy an application's complex synchronization requirements. a ser...lane[2:0]p lane[2:0]n avss (pll) ovdd (pll) dnc avdd 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 ... |
| Description |
Dual 14-Bit, 250/200/125 MSPS JESD204B High Speed Serial Output ADC
|
| File Size |
2,068.73K /
38 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
Integrated Device Techn...
|
| Part No. |
89HPES34H16G2
|
| OCR Text |
...as two independent buses; thus, multi-master arbitration is not required. bit slave smbus address master smbus address 1 ssmbaddr[1] msmbadd...lane to lane input skew 20 8 ns t rx-hf-rms 1.5 ? 100 mhz rms jitter (common clock) na 3.4 ps t rx-h... |
| Description |
Low latency cut-through architecture
|
| File Size |
353.61K /
54 Page |
View
it Online |
Download Datasheet |
| |
|
|
Integrated Device Techn...
|
| Part No. |
89HPES34H16
|
| OCR Text |
... two independent buses and thus multi-master arbitration is never required. the pes34h16 supports reading and writing of the serial eeprom o...lane to lane input skew 20 ns table 10 pcie ac timing characteristics
16 of 45 october 3, 2011 i... |
| Description |
Sixteen maximum switch ports
|
| File Size |
327.32K /
45 Page |
View
it Online |
Download Datasheet |
| |
|
|
IDT
|
| Part No. |
89PES5T5
|
| OCR Text |
... two independent buses and thus multi-master arbitration is never required. the pes5t5 supports reading and writing of the serial eeprom on...lane 30 80 ns t rxdetecten pulse width of rxdetecten input 9.8 10 10.2 ns t rxdetect rxdetecten fall... |
| Description |
5-Lane 5-Port PCI Express Switch
|
| File Size |
283.56K /
26 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
