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GSI Technology, Inc.
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| Part No. |
GS832136GE-133I
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| OCR Text |
...reset inputs a i address inputs dq a dq b dq c dq d i/o data input and output pins b a , b b , b c , b d i byte write enable for dq a , dq b , dq c , dq d i/os; active low nc ? no connect ck i clock input signal; active high bw i byte w... |
| Description |
2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 1M X 36 CACHE SRAM, 8.5 ns, PBGA165
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| File Size |
733.77K /
32 Page |
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it Online |
Download Datasheet
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Hanbit Electronics Co., Ltd.
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| Part No. |
HDD32M72B9-13A HDD32M72B9-13B HDD32M72B9-16B
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| OCR Text |
...with sstl_2 interface ? data(dq), data strobes and write masks latched on the rising and falling edge s of the clock ? all addres...m v) (ps) (ps) 280 +50 +50 this derating t able is used to increase tds/tdh in the case... |
| Description |
DDR SDRAM Module 256Mbyte (32Mx72bit), based on32Mx8,4Banks, 8K Ref., ECC Unbuffered SO-DIMM 256MB的DDR SDRAM内存模块2Mx72bit）根据on32Mx8BanksK的参考。，ECC无缓冲的SO - DIMM
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| File Size |
200.80K /
12 Page |
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it Online |
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GSI Technology, Inc.
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| Part No. |
GS881Z18T-11I GS881Z18T-66I GS881Z36T-80
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| OCR Text |
... 26 27 28 29 30 v ddq v ss dq b1 dq b2 v ss v ddq dq b3 dq b4 ft v dd dp v ss dq b5 dq b6 v ddq v ss dq b7 d...m s t d i v s s v d d t d o t c k a 1 0 a 1 1 a 1 2 a 1 3 a 1 4 a 1 6 a 6 a 7 e 1 e 2 ... |
| Description |
8Mb Pipelined and Flow Through Synchronous NBT SRAMs 512K X 18 ZBT SRAM, 11 ns, PQFP100
8Mb Pipelined and Flow Through Synchronous NBT SRAMs 512K X 18 ZBT SRAM, 18 ns, PQFP100
8Mb Pipelined and Flow Through Synchronous NBT SRAMs 256K X 36 ZBT SRAM, 14 ns, PQFP100
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| File Size |
536.96K /
34 Page |
View
it Online |
Download Datasheet |
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GSI Technology, Inc.
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| Part No. |
GS8321V36E-133 GS8321V36E-133I GS8321V36E-166I GS8321V3GE-200 GS8321V18E-166 GS8321V18E-166I GS8321V36GE-166 GS8321V36GE-166I GS8321V32E-133I GS8321V36GE-250I GS8321V18GE-166 GS8321V32GE-166I GS8321V32E-250 GS8321V18E-225I GS8321V18E-133 GS8321V18E-133I
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| OCR Text |
...reset inputs a i address inputs dq a dq b dq c dq d i/o data input and output pins b a , b b , b c , b d i byte write enable for dq a , dq b , dq c , dq d i/os; active low nc ? no connect ck i clock input signal; active high bw i byte w... |
| Description |
2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 1M X 36 CACHE SRAM, 8.5 ns, PBGA165
2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 1M X 36 CACHE SRAM, 8 ns, PBGA165
2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 200万1800万3200万36同步突发静态存储器分配36MB
2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 2M X 18 CACHE SRAM, 8 ns, PBGA165
2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 1M X 32 CACHE SRAM, 8.5 ns, PBGA165
2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 1M X 36 CACHE SRAM, 6.5 ns, PBGA165
2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 1M X 32 CACHE SRAM, 8 ns, PBGA165
2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 1M X 32 CACHE SRAM, 6.5 ns, PBGA165
2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 2M X 18 CACHE SRAM, 7 ns, PBGA165
2M x 18, 1M x 32, 1M x 36 36Mb Sync Burst SRAMs 2M X 18 CACHE SRAM, 8.5 ns, PBGA165
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| File Size |
729.65K /
31 Page |
View
it Online |
Download Datasheet |
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