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Xilinx
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| Part No. |
XCV50E
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| OCR Text |
...y of configurable logic blocks (clbs) sur- rounded by programmable input/output blocks (iobs), all interconnected by a rich hierarchy of fast, versatile routing table 1: virtex-e field-programmable gate array family members device system... |
| Description |
Virtex-e Field Programmable Gate Array
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| File Size |
1,827.67K /
233 Page |
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XILINX[Xilinx, Inc]
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| Part No. |
XC3090L XC3000L XC3020L XC3030L XC3042L XC3064L
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| OCR Text |
...030L XC3042L XC3064L XC3090L
clbs 64 100 144 224 320
Array 8x8 10 x 10 12 x 12 16 x 14 16 x 20
User I/Os Max 64 80 96 120 144
Flip-Flops 256 360 480 688 928
Horizontal Longlines 16 20 24 32 40
Configurable Data Bits 14,779... |
| Description |
Part of the ZERO family of 3.3 V FPGAs
XC3000L Low Voltage Logic Cell Array Family
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| File Size |
47.60K /
8 Page |
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it Online |
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XILINX[Xilinx, Inc]
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| Part No. |
XC3195A XC3100A XC3120A XC3130A XC3142A XC3164A XC3190A
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| OCR Text |
...142A XC3164A XC3190A XC3195A
clbs 64 100 144 224 320 484
Array 8x8 10 x 10 12 x 12 16 x 14 16 x 20 22 x 22
User I/O Max 64 80 96 120 144 176
Flip-Flops 256 360 480 688 928 1,320
Horizontal Longlines 16 20 24 28 40 44
Confi... |
| Description |
Ultra-high-speed FPGA family with six members
Logic Cell Array Families
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| File Size |
62.82K /
8 Page |
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it Online |
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Price and Availability
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