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phase-aligned Datasheet PDF File

For phase-aligned Found Datasheets File :: 1211 Search Time::1.157ms
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				Agilent (Hewlett-Packard) HP[Agilent(Hewlett-Packard)]
Part No.	HDMP-1687
OCR Text	... TTL parallel I/Os High-speed phase locked loops Parallel-to-serial converter High-speed serial clock and data recovery circuitry * Comma ...aligned, as shown in Figure 3. RFCT is also used as a clean frequency reference for the receiver PLL...
Description	HDMP-1687 · 1.0625-1.25 GBd Four Channel SerDes for Fibre Channel and Gigabit Ethernet Applications Four Channel SerDes Circuit for Gigabit Ethernet and Fibre Channel
File Size	336.90K / 16 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY23FS08OC CY23FS08OCT CY23FS08OI CY23FS08OIT CY23FS08OXC CY23FS08OXCT CY23FS08OXI CY23FS08OXIT CY23FS0806
OCR Text	... outputs * 5V-tolerant inputs * Phase-locked loop (PLL) Bypass Mode * Dual Reference Inputs * 28-pin SSOP * Split 2.5V or 3.3V output power ...aligned outputs. The device provides an optimum solution for applications where continuous operation...
Description	Failsafe 2.5V/ 3.3V Zero Delay Buffer Failsafe⑩ 2.5V/ 3.3V Zero Delay Buffer
File Size	267.31K / 12 Page	View it Online	Download Datasheet

				Cypress Semiconductor, Corp.
Part No.	CY23FS08-04 CY23FS08OXI-04 CY23FS08OXI-04T
OCR Text	...eference clock inputs and eight phase aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. Continuous, glitch free operation is achieved by...
Description	133 MHz, OTHER CLOCK GENERATOR, PDSO28 5.30 MM, LEAD FREE, SSOP-28 FailSafe⑩ 1.8V Zero Delay Buffer FailSafe 1.8V Zero Delay Buffer
File Size	256.03K / 11 Page	View it Online	Download Datasheet

				Cypress Semiconductor, Corp.
Part No.	CY23FS08OXC CY23FS08OXCT CY23FS08OXIT CY23FS0811 CY23FS0812
OCR Text	...) outputs 5 v-tolerant inputs phase-locked loop (pll) bypass mode dual reference inputs 28-pin ssop split 2.5 v or 3.3 v output power ...aligned outputs. the device provides an optimum solution for applications where continuous operation...
Description	Failsafe 2.5 V/3.3 V Zero Delay Buffer Failsafe 2.5V/ 3.3V Zero Delay Buffer 166.7 MHz, OTHER CLOCK GENERATOR, PDSO28 Failsafe?2.5 V/3.3 V Zero Delay Buffer
File Size	346.25K / 15 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY2303 CY2303SC CY2303SCT CY2303SI CY2303SIT CY2303SXC CY2303SXCT CY2303SXI CY2303SXIT
OCR Text	phase-aligned Clock Multiplier Features * 3-multiplier configuration (1x, 2x, 4x Ref) * 10 MHz to 166.67 MHz operating range (reference input from 10 MHz to 41.67 MHz) * Phase Alignment * 80 ps typical period jitter * Output enable pin * ...
Description	phase-aligned Clock Multiplier
File Size	123.40K / 7 Page	View it Online	Download Datasheet

				Microchip Technology
Part No.	DSPIC33FJ12MC201TIML DSPIC33FJ12MC202TIML DSPIC33FJ12MC201TEML DSPIC33FJ12MC201TESO DSPIC33FJ12MC201TESS DSPIC33FJ12MC201TESP DSPIC33FJ12MC202TESP DSPIC33FJ12MC202TISO DSPIC33FJ12MC202TISP DSPIC33FJ12MC202TISS
OCR Text	... internal rc - fully integrated phase-locked loop (pll) - extremely low-jitter pll ? power-up timer ? oscillator start-up timer/stabilizer ?...aligned or center-aligned - manual output override control - one fault input - trigger for adc conve...
Description	High-Performance, 16-bit Digital Signal Controllers
File Size	2,281.76K / 304 Page	View it Online	Download Datasheet

				ZARLINK[Zarlink Semiconductor Inc]
Part No.	MT8941BPR1 MT8941 MT8941BE MT8941BP MT8941BP1 MT8941BPR
OCR Text	... The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and...aligned with either the falling or the rising edge of CS. It is aligned with the rising edge of CS w...
Description	Advanced T1/CEPT Digital Trunk PLL
File Size	476.91K / 27 Page	View it Online	Download Datasheet

				Agilent (Hewlett-Packard) Agilent(Hewlett-Packard)
Part No.	HDMP-1646A HDMP-1636A HDMP-T1636A
OCR Text	...ks which are 180 degrees out of phase with each other. For Gigabit Ethernet, these clocks are 62.5 MHz, whereas for Fibre Channel, they are 53.125 MHz. The parallel data is properly aligned with the rising edge of alternating clocks. For te...
Description	HDMP-T1636A · 1.0625-1.25 GBd SerDes IC in 10 mm TQFP for Fibre Channel/Storage and Gigabit Ethernet Applications HDMP-1646A · 1.0625-1.25 GBd SerDes IC in 14 mm PQFP for Fibre Channel/Storage and Gigabit Ethernet Applications HDMP-1636A · 1.0625-1.25 GBd SerDes IC in 10 mm PQFP for Fibre Channel/Storage and Gigabit Ethernet Applications 1.0625-1.25GBdSerDesICin14mmPQFPforFibreChannel/StorageandGigabitEthern.. Gigabit Ethernet and Fibre Channel SerDes ICs
File Size	278.71K / 18 Page	View it Online	Download Datasheet

For phase-aligned Found Datasheets File :: 1211 Search Time::1.157ms
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