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Zarlink Semiconductor, Inc.
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| Part No. |
ZL50019QCG1
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| OCR Text |
...ated digital phase-locked loop (dpll) exceeds telcordia gr-1244-core stratum 4e specifications ? output clocks have less than 1 ns of jitter (except for the 1.544 mhz output) ? dpll provides holdover, freerun and jitter attenuation feat... |
| Description |
Enhanced 2 K Digital Switch with Stratum 4E dpll TELECOM, DIGITAL TIME SWITCH, PQFP256
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| File Size |
926.88K /
121 Page |
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Mitel Networks, Corp.
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| Part No. |
MT9041BP
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| OCR Text |
...ns a digital phase-locked loop (dpll), which provides timing and synchronization signals for multitrunk t1 and e1 primary rate transmission links. the mt9041b generates st-bus clock and framing signals that are phase locked to either a 2.04... |
| Description |
T1/E1 System Synchronizer T1/E1的系统同
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| File Size |
76.88K /
19 Page |
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it Online |
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Zarlink
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| Part No. |
MT9040
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| OCR Text |
...ns a digital phase-locked loop (dpll), which provides timing and synchronization signals for T1 and E1 primary rate transmission links. The MT9040 generates ST-BUS clock and framing signals that are phase locked to either a 19.44 MHz, 2.048... |
| Description |
T1/E1 Synchronizer
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| File Size |
373.11K /
28 Page |
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it Online |
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Zarlink Semiconductor, Inc.
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| Part No. |
ZL50010GDG2
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| OCR Text |
...ated digital phase-locked loop (dpll) meets telcordia gr-1244-core stratum 4 enhanced specifications ? dpll provides automatic reference switching, jitter attenuation, holdover and free run functions ? per-stream st-bus input with data ... |
| Description |
Flexible 512 Channel DX with Enhanced dpll TELECOM, DIGITAL TIME SWITCH, PBGA144
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| File Size |
706.45K /
87 Page |
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it Online |
Download Datasheet |
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Zarlink Semiconductor, Inc.
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| Part No. |
ZL30110
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| OCR Text |
...ystal or oscillator ? provides dpll lock and reference fail indication ? automatic free run mode on reference fail ? dpll bandwidth of 922 hz for all rates of input reference and 58 hz for an 8 khz input reference ? less than 5 psec rms ... |
| Description |
Telecom Rate Conversion dpll 电信速率转换数字锁相
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| File Size |
262.53K /
21 Page |
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it Online |
Download Datasheet |
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Zarlink
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| Part No. |
MT9042C
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| OCR Text |
...ns a digital phase-locked loop (dpll), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9042C generates ST-BUS clock and framing signals that are phase locked to either a 2.04... |
| Description |
Multitrunk System Synchronizer
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| File Size |
533.79K /
28 Page |
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it Online |
Download Datasheet |
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Zarlink
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| Part No. |
MT9046
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| OCR Text |
...ns a digital phase-locked loop (dpll), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The device has reference switching and frequency holdover capabilities to help maintain conne... |
| Description |
T1/E1 System Synchronizer with Holdover
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| File Size |
430.33K /
34 Page |
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it Online |
Download Datasheet |
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IDT
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| Part No. |
IDT82V3002A
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| OCR Text |
...ns a Digital Phase-Locked Loop (dpll), which generates ST-BUS clocks and framing signals that are phase locked to a 2.048 MHz, 1.544 MHz or 8 kHz input reference. The IDT82V3002A provides eight types of clock signals (C1.5o, C3o, C6o, C2o, ... |
| Description |
WAN PLL WITH DUAL REFERENCE INPUTS
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| File Size |
330.42K /
28 Page |
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it Online |
Download Datasheet |
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Price and Availability
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